(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming salicided gate electrodes whereby no danger exists of having an electrical short between the gate contact and the contacts for the source and drain regions.
(2) Description of the Prior Art
With the continued demand for improved device performance comes a continued emphasis on decreasing device dimensions. Decreasing semiconductor dimensions provides the dual advantages of being able to dramatically increase device density and of significantly improving device performance. Device performance is improved with decreasing device dimensions because decreased device dimensions results in shorter paths that need to be traveled by charge carriers such as electrons. This is for instance the case in the creation of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) gate electrodes that have as electrical points of contact the gate surface and the source and drain regions. The distance between the source and drain regions forms the channel length of the gate electrode, by decreasing device dimensions the channel length is accordingly decreased resulting in a shorter path between the source and the drain regions. The result is that the switching speed of the device is increased. It is self evident that reducing device dimensions results in increased packaging density of devices o n a semiconductor chip. This increased packaging density brings with it sharp reductions in the length of the interconnect paths between devices, which reduces the relative negative impact (such as resistive voltage drop, cross talk or RC delay) that these interconnect paths have on overall device performance.
Reducing device dimensions requires that the Critical Dimensions (CD) of the device are reduced. The ability to continue the reduction of device CD's depends to a considerable degree on the resolution capability of the technologies, such as photolithography, that are used in masking and etching device features. In order to create for instance the gate structure of a gate electrode, a layer of gate material such as polysilicon is etched after a layer of photoresist has been deposited over the surface of the layer of poly and has been exposed to a light source and etched. The photoresist that is used for this purpose is typically a positive photoresist, this layer of photoresist is exposed to a light source using a mask that contains opaque features. Where the light strikes the opaque features, the mask blocks the light so that the incident light will not reach the layer of photoresist. Where the mask is not opaque, the incident light will pass through the mask and strike the layer of photoresist. The chemical composition of the layer of photoresist is sensitive to certain wavelengths of light. With a positive layer of photoresist, the chemical composition of the photoresist that has been subjected to the incident light is changed such that the photoresist becomes soluble and can therefore be removed by a developer. The region of the layer of photoresist under which the poly gate structure of the gate electrode needs to be formed was not exposed by the incident light, the surrounding region of the layer of photoresist was exposed and can therefore be removed. The layer of poly that remains covered with photoresist is the region of the poly that forms the gate structure, since this region is now protected by the overlying layer of photoresist, the surrounding regions of the layer of poly can be etched away leaving only enough poly in place to form the structure of the gate electrode. The body or structure of the gate electrode can contain polysilicon but can also contain refractory metals, silicides and other conductive materials while doped polysilicon can also be used.
The process of photolithography that is used to expose the layer of photoresist typically uses mercury vapor lamps as the source of illumination with a wavelength of between about 390 and 450 nm. These sources of light exposure are frequently used in conjunction with I-line steppers, image reduction systems and other optical devices that are aimed at further improving exposure quality by improving exposure resolution and depth of focus. In applying masks for the creation of device features, the resolution of these device features is limited by the CD's of the mask that is applied in this process. Development is under way to create more advanced methods of exposure that apply such technologies as electron beam lithography, x-ray lithography and ion beam lithography. E-beam lithography uses a narrow stream of electrons that scribes a pattern in a layer of E-beam sensitive material, this method has allowed for feature size down to 0.1 um. Ion beam lithography does not have the inherent disadvantage of E-beam lithography of difficulty in concentrating a narrow stream of electrons. Ions are heavier than electrons and therefore are easier to project in a concentrated stream. X-ray lithography holds promise but suffers from the inherent limitation that X-rays, due to their smaller wavelength, are difficult to control. Future developments in all of these areas continue and are consistently aimed at providing the ability to reduce semiconductor device CD's into the sub-micron range, that is in the range of 0.20 um or less.
As previously stated, higher device performance and improved functional capacity in integrated circuits require reduction of device CD's and increased packaging density of the devices. Such requirements however cause problems of increased parasitic capacitance, device contact resistance (gate, source and drain contacts in MOSFET devices), and tight tolerance of pattern definition. Silicides are often used to reduce contact resistance. For very small sub-micron or sub-half-micron or even sub-quarter-micron modern silicon devices, conventional photolithographic technique for patterning contacts will not meet the required tolerance of critical dimensions. Methods that are being explored to improve resolution and feature size of applicable projection methods have been briefly highlighted above. In addition, in forming contact points to the gate electrode of a MOSFET device, the method of self-aligned silicide (salicide) formation helps to solve the problem of critical dimension tolerance. Using this method, the contact points that are formed for the source and the drain of the gate electrode self-align with the polysilicon gate. Salicides are therefore almost universally applied in today's high-density MOSFET devices. There are, however, problems associated with methods of salicide formation. One main problem is that the salicidation process of converting a refractory metal to its silicide is achieved by the consumption of silicon underlying the metal resulting in the consumption of substrate silicon in the regions of the source and drain. The source/drain junctions of sub-half-micron MOSFET devices are very shallow, the consumption of silicon in the source/drain regions can therefore result in source/drain regions that are extremely thin. A further and very severe problem is that the salicidation reaction can consume substrate silicon unevenly, leading to ragged source/drain junctions and, even worse, the creation of spikes that can penetrate through the junctions near the edges of the source/drain areas. Another problem that is directly related to the reduction in device CD's is that electrical shorts can occur between the contact points that are formed over the gate structure and the source/drain regions. The process of salicidation is followed by the removal of the unreacted metal from the gate spacers that have been formed over sidewalls of the gate electrode structure. If this removal is incomplete or not properly aligned, shorts are likely to occur between the layers of silicide that have been formed over the gate structure and the source/drain regions. It is therefore, with ever smaller device dimensions, becoming increasingly more difficult to create gate and source/drain points of electrical contact while maintaining the required low sheet resistance and low junction leakage current for the contact points. As salicides, both TiSi2 and CoSi2 can be used for the layer of metal from which the salicided contact points are formed. Both of these materials have low sheet resistivity. Of these two materials, CoSi2 is the most promising for the formation of silicided layers of contact, especially for the extremely small device CD's that will be required in future devices. The problem of gate and source/drain bridging that has been highlighted above must however be addressed when using CoSi2 as a metal for the salicidation process. The invention addresses this concern.
The formation of an n-type channel MOS device that has salicided source/drain contacts in addition to a salicided gate electrode will be detailed below. FIG. 1 shows a cross section of a p-type semiconductor surface 10, field isolation regions 11 of thick oxide have been provided in the surface of the substrate to define the active region of the substrate. A thin layer 12 of gate oxide has been formed using methods of thermal oxidation, a layer 14 of polysilicon is deposited over the surface of the gate oxide layer 12, this deposited layer 14 of poly is provided with a n-type conductivity and patterned to form the body of the gate electrode. The etch that is required to form the body of the gate electrode removes the deposited layer of poly and the deposited layer of gate oxide in accordance with the pattern of the gate electrode. An n-type ion implant 18 is performed into the surface of the substrate, this implant is self-aligned with the body 14 of the gate electrode and forms the LDD regions of the gate electrode. The gate spacers 16 are next formed by a blanket CVD deposition of a layer of silicon oxide over the surface of the gate electrode and its surrounding area, the layer 16 of silicon oxide is anisotropically etched back thereby forming the gate spacers 16 on the sidewalls of the gate electrode. A second, relatively deep and heavily doped n-type implant 20/21 is performed into the surface of the substrate 10 to form the source and drain regions 20/21 of the gate electrode 14. The region 18 of the LDD is now concentrated under the spacers 16 of the gate electrode. The next step in the process is the step of forming contacts with the gate electrode source (20) and drain (21) regions and the surface of the gate electrode 14. A layer 24 of refractory metal is blanket deposited over the entire structure. The structure that is shown in FIG. 1 is subjected to a heat treatment that causes layer 24 to react with the underlying layer 14 of poly and the underlying surface of the source and drain regions 20 and 21 whereby this layer of refractory metal 24 is fully converted to a silicide. The unreacted refractory metal has not formed silicide and is therefore removed by applying a selective etch that essentially removes the metal from the surface of the gate electrode spacers 16 leaving the silicided metal in place over the surface of the source 20 and drain 21 regions in addition to leaving the silicided metal in place over the surface of the gate electrode 14. A cross section of the gate structure after the unreacted refractory metal has been removed from the structure is shown in FIG. 2 where the layers 24 form the points of electrical contact to the gate electrode and the source and drain regions of this gate electrode.
FIG. 3 shows how the gate electrode of the Prior Art can be completed by depositing a layer 26 of dielectric over the surface of the structure that is shown in cross section in FIG. 2, by etching openings 27, 28 and 29 through this layer 26 of dielectric whereby (FIG. 3) opening 27 overlays and aligns with the source region 20 of the gate electrode, opening 28 overlays and aligns with the top surface of the gate electrode 14 and opening 29 overlays and aligns with the drain region 21 of the gate electrode. A layer of metal is then blanket deposited over the surface of the layer 26 of dielectric thereby including the openings 27, 28 and 29. This latter layer of metal is patterned and etched thereby creating the electrical contact 30 with the source region 20 of the gate electrode, contact 31 with the top surface of the gate electrode and contact 32 with the drain region 21 of the gate electrode. These three electrical contact points are typically connected to a surrounding network of interconnect metal lines.
U.S. Pat. No. 5,824,588 (Liu) shows a double spacer (oxide/oxide) salicide process.
U.S. Pat. No. 5,851,890 (Tsai et al.) teaches a double spacer (oxide/SiN) salicide process. This appears to show the invention except for the removal of the SiN spacer. This is extremely close to the invention.
U.S. Pat. No. 5,679,589 (Lee et al.) shows a salicide process with double spacers (e.g., oxide/SiN).
U.S. Pat. No. 5,668,024 (Tsai et al.) teaches a double spacer process (oxide/TiN) salicide process where the second spacer is removed as in the invention. This patent appears to differ from the invention only the composition of the 2'd spacer (TiN vs invention's SiN).